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pedl66577-01 1 semiconductor this version: apr. 2000 msm66577 family preliminary 16-bit microcontroller 1/34 general description the msm66577 family of highly functional cmos 16-bit single chip microcontrollers utilizes the nx-8/500s, oki?s proprietary cpu core. four channels of serial ports, consisting of two channels of synchronous serial ports with 32-byte fifo registers and two channels of uart/synchronous serial ports, enable easy interfacing with external peripheral lsi devices such as an encoder/decoder or servocontroller. a switching function permits selection of separate address and data lines or multiplexed lines for the external bus interface to correspond to various peripheral lsi devices. with features such as a clock gear function, dual clock function, stop/halt mode, programmable pull-up ports in which individual bits can be programmed, and a small, thin package, the msm66577 family of microprocessors is optimally suited for the system control of small-sized low power devices. the flash rom version (msm66q577ly) programmable with a single 3v power supply (3.0 to 3.6v) and flash rom version (msm66q577) programmable with a single 5v power supply (4.5 to 5.5v) are also included in the family. these versions are easily adaptable to sudden specification changes and to new product versions. applications digital audio control systems pc peripheral control systems office electronics control systems ordering information order code or product name package remark msm66577l-xxtb *1 low voltage mask rom version (2.4 to 3.6 v) MSM66577-XXTB *1 5 v mask rom version (4.5 to 5.5 v) msm66q577ly-ntb *2 msm66577l flash rom version (3.0 to 3.6v) msm66q577-ntb *2 100-pin plastic tqfp (tqfp 100-p-1414-0.50-k) msm66577 flash rom version (4.5 to 5.5 v) *1 : the ?xx? of ?-xx? stands for the code number. *2 : the ?n? of ?-n? stands for the flash rom and the otp rom, blank version. when oki programs and ship the flash rom and otp, the part number is changed from ??n? to ??xx? (code number ) , for example, msm66q577-999tb.
pedl66577-01 1 semiconductor msm66577 family 2/34 features name msm66577l msm66577 operating temperature ?30c to +70c power supply voltage/ maximum frequency v dd = 2.4 to 3.6 v/f = 14 mhz v dd = 4.5 to 5.5 v/f = 30 mhz 143 ns at 14 mhz 67 ns at 30 mhz minimum instruction execution time 61 s at 32.768 khz internal rom size (max. external) 128 kb (1 mb) internal ram size (max. external) 4 kb (1 mb) i/o ports 74 i/o pins (with programmable pull-up resistors) 8 input-only pins 16-bit free running timer 1ch compare output/capture input 2ch 16-bit timer (auto reload/timer out) 1ch 8-bit auto reload timer 2ch (can also be used as 16-bit timer 1ch) 8-bit auto reload timer 1ch 8-bit auto reload timer 3ch (also functions as serial communication baud rate generator) 8-bit auto reload timer 1ch (also functions as watchdog timer) watch timer (real-timer counter) 1ch timers 8-bit pwm 4ch (can also be used as 16-bit pwm 2ch) synchronous, with 32-byte fifo 2ch serial port uart/synchronous 2ch a/d converter 10-bit a/d converter 8ch d/a converter 8-bit d/a converter 2ch external interrupt non-maskable 1ch maskable 8ch interrupt priority 3 levels external bus interface (separate address and data busses / multiplexed address and data busses) bus release function dual clocks function others clock gear function flash rom version msm66q577ly (v dd =3.0 to 3.6v) msm66q577
pedl66577-01 1 semiconductor msm66577 family 3/34 special features 1. high-performance cpu the family includes the high-performance cpu, powerful bit manipulation instruction set, full symmetrical addressing mode, and rom window function, and also provides the best optimized c compiler support. 2. a variety of power saving modes attaching a 32.768-khz crystal produces a real-time clock signal from the internal clock timer. use of a single clock in place of dual clocks is possible. the clock gear function allows a 1/2 or 1/4 main clock to be selected for the cpu operating clock. switching the cpu clock to 32.768-khz signal, 1/2 main clock, or 1/4 main clock, then produces operation in a low power consumption mode. the family provides a wide range of standby control functions. in addition to the usual stop mode that stops the oscillator, there are the quick restart stop mode that shuts down the cpu and peripherals but leaves the oscillator running, and the halt mode that shuts down the cpu but leaves the peripherals running. 3. variety of multifunctional serial ports the family includes two channels of built-in synchronous serial ports with 32-byte fifo implementing an auto transfer function. the family allows multi-byte 1-frame information which consists of address, command, and data to be easily and efficiently transmitted to or received from a serial interface type peripheral lsi device. the family also allows multi-byte character information to be easily and efficiently transmitted to or received from an lcd module. in addition, the family has two channels of combined uart/synchronous serial ports, and provides four channels of serial interfaces. 4. msm66q577ly and msm66q577 with flash memory programmable with single power supply in addition to the regular mask rom version, the family includes these versions with 128kb of flash memory that can be programmed using a single power supply. for the msm66q577ly, an internal booster circuit derives the necessary program voltage from the device's low (3.0 to 3.6v) power supply, and the program voltage for the msm66q577 is provided with a single 5 v power supply (4.5 to 5.5 v). 5. high-precision a/d and d/a converters the family includes a high-precision 10-bit analog-to-digital converter with eight channels and 8-bit digital-to- analog converter with two channels. uart/synchronous sio uart/synchronous sio synchronous sio with 32-byte fifo synchronous sio with 32-byte fifo
pedl66577-01 1 semiconductor msm66577 family 4/34 6. multifunction pwm the family supports both 8- and 16-bit pwm operation. choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the pwm counter clock source provides a wide number of possibilities over a broad frequency range. the 16-bit pwm configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog control applications. 7. programmable pull-up resistors building the pull-up resistors into the chip contributes to overall design compactness. making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. these programmable pull-up resistors are available for all i/o pins not already assigned specific functions (such as the oscillator connection pins). 8. wide support for external interrupts there are a total of nine interrupt channels for use in communicating with external devices: eight for maskable interrupts and one for non-maskable interrupts.
pedl66577-01 1 semiconductor msm66577 family 5/34 block diagram *: address output/data i/o when selecting multiplexed bus type. nmi exint0 to exint7 tm4out sioi4 sioo4 siock4 pwmout0 pwmout2 pwmout1 pwmout3 cpcm0 cpcm1 sioi5 sioo5 siock5 ao0 ao1 instruction decoder ram 4k tbc rtc tm0out tm0evt tm1out tm1evt tm2out tm2evt clkout xtout cpu core port control rom 128k bus port control rxd1 txd1 rxc1 txc1 1 6 b i t tim e r 0 p e ri p h e r a l sio1 (uart/sync) 8 b i t tim e 4 / br g 8 bit pwm0 8 bit pwm1 sio4 ( 32 b y te fifo sync ) 8 b i t tim e r 3/ br g 8 b i t tim e r 6/ wd t 8bittimer9 c ap /c mp 1 6 b i t fr c 10 bit a/d converter interrupt v ref agnd ai0 to ai7 alu control acc p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p14 p15 system control memory control pointing registers local registers ssp lrb psw pc dsr tsr csr control registers alu ea selmbus psen rd wr wait d0 to d7 a0 to a19 xt0 xt1 osc0 osc1 hold hldack res 8 bit timer1 8 bit timer2 rxd6 txd6 rxc6 txc6 sio6 (uart/sync) sio5 ( 32 b y te fifo sync ) 8 b i t d / a co nv e r te r (ad0 to ad7*) 8 b i t tim e r 5/ br g
pedl66577-01 1 semiconductor msm66577 family 6/34 pin configuration (top view) siock4/p10-3 sioo4/p10-4 sioi4/p10-5 rxd1/p8-0 txd1/p8-1 rxc1/p8-2 txc1/p8-3 tm4out/p8-4 pwm2out/p8-6 pwm3out/p8-7 pwm0out/p7-6 pwm1out/p7-7 v dd gnd hldack/p9-7 exint4/p9-0 exint5/p9-1 exint6/p9-2 exint7/p9-3 exint0/p6-0 exint1/p6-1 exint2/p6-2 exint3/p6-3 tm1evt/p6-4 tm1out/p6-5 p1-6/a14 p1-5/a13 p1-4/a12 p1-3/a11 p1-2/a10 p1-1/a9 p1-0/a8 p4-7/a7 p4-6/a6 p4-5/a5 p4-4/a4 p4-3/a3 p4-2/a2 p4-1/a1 p4-0/a0 gnd p0-7/d7(ad7*) p0-6/d6(ad6*) p0-5/d5(ad5*) p0-4/d4(ad4*) p0-3/d3(ad3*) p0-2/d2(ad2*) p0-1/d1(ad1*) p0-0/d0(ad0*) p3-3/wr p3-2/rd p3-1/psen p3-0/ale selmbus p11-3/xtout p11-2/clkout p11-1/hold p11-0/wait v dd osc1 osc0 gnd xt1 xt0 v dd ea nmi res p5-7/tm0evt p5-6/tm0out p5-5/cpcm1 p5-4/cpcm0 p6-7/tm2out p6-6/tm2evt a16/p2-0 a17/p2-1 a18/p2-2 a19/p2-3 v dd v ref ai0/p12-0 ai1/p12-1 ai2/p12-2 ai3/p12-3 ai4/p12-4 ai5/p12-5 ai6/p12-6 ai7/p12-7 agnd ao1/p14-7 ao0/p14-6 gnd sioi5/14-2 sioo5/p14-1 siock5/p14-0 rxd6/p15-0 txd6/p15-1 rxc6/p15-2 txc6/p15-3 80 85 90 95 100 1 5 10 15 20 25 75 70 65 60 55 50 45 40 35 30 p1-7/a15 100-pin plastic tqfp *: address output/data i/o when selecting multiplexed bus type.
pedl66577-01 1 semiconductor msm66577 family 7/34 pin descriptions in the type column, ?i? indicates an input pin, ?o? indicates an output pin, and ?i/o? indicates an i/o pin. description function symbol type primary function type secondary function p0_0/d0 (ad0) to p0_7/d7 (ad7) i/o 8-bit i/o port 10 ma sink capability pull-up resistors can be specified for each individual bit i/o external memory access data i/o port (address output/data i/o port when selecting a multiplexed bus) p1_0/a8 to p1_7/a15 i/o 8-bit i/o port pull-up resistors can be specified for each individual bit o external memory access address output port p2_0/a16 to p2_3/a19 i/o 4-bit i/o port pull-up resistors can be specified for each individual bit o external memory access address output port p3_0/ale o external memory access address latch enable signal output pin p3_1/ psen o external program memory access read strobe output pin p3_2/ rd o external memory access read strobe output pin p3_3/ wr i/o 4-bit i/o port 10 ma sink capability pull-up resistors can be specified for each individual bit o external memory access write strobe output pin p4_0/a0 to p4_7/a7 i/o 8-bit i/o port pull-up resistors can be specified for each individual bit o external memory access address output port (when selecting a separate bus type) p5_4/cpcm0 i/o capture 0 input / compare 0 output pin p5_5/cpcm1 i/o capture 1 input / compare 1 output pin p5_6/tm0out o timer 0 timer output pin p5_7/tm0evt i/o 4-bit i/o port pull-up resistors can be specified for each individual bit i timer 0 external event input pin p6_0/exint0 i external interrupt 0 input pin p6_1/exint1 i external interrupt 1 input pin p6_2/exint2 i external interrupt 2 input pin p6_3/exint3 i external interrupt 3 input pin p6_4/tm1evt i timer1 external event input pin p6_5/tm1out o timer 1 timer output pin p6_6/tm2evt i timer 2 external event pin port p6_7/tm2out i/o 8-bit i/o port pull-up resistors can be specified for each individual bit o timer 2 timer output pin
pedl66577-01 1 semiconductor msm66577 family 8/34 description function symbol type primary function type secondary function p7_6/pwm0out o pwm0 output pin p7_7/pwm1out i/o 2-bit i/o port pull-up resistors can be specified for each individual bit o pwm1 output pin p8_0/rxd1 i sio1 receive data input pin p8_1/txd1 o sio1 transmit data output pin p8_2/rxc1 i/o sio1 receive clock i/o pin p8_3/txc1 i/o sio1 transmit clock i/o pin p8_4/tm4out o timer 4 timer output pin p8_6/pwm2out o pwm2 output pin p8_7/pwm3out i/o 7-bit i/o port pull-up resistors can be specified for each individual bit o pwm3 output pin p9_0/exint4 i external interrupt 4 input pin p9_1/exint5 i external interrupt 5 input pin p9_2/exint6 i external interrupt 6 input pin p9_3/exint7 i external interrupt 7 input pin p9_7/hldack i/o 5-bit i/o port pull-up resistors can be specified for each individual bit o hold mode output pin p10_3/siock4 i/o sio4 transmit-receive clock i/o pin p10_4/sioo4 i sio4 receive data input pin p10_5/sioi4 i/o 3-bit i/o port pull-up resistors can be specified for each individual bit o sio4 transmit data output pin p11_0/wait i external data memory access wait input pin p11_1/hold i hold mode request input pin p11_2/clkout o main clock pulse output pin p11_3/xtout i/o 4-bit i/o port 10 ma sink capability pull-up resistors can be specified for each individual bit o sub clock pulse output pin p12_0/ai0 to p12_7/ai7 i 8-bit input port i a/d converter analog input port p14_0/siock5 i/o sio5 transmit-receive clock i/o pin p14_1/sioo5 o sio5 transmit data output pin p14_2/sioi5 i sio5 receive data input pin p14_6/ao0 o d/a converter analog output port p14_7/ao1 i/o 5-bit i/o port pull-up resistors can be specified for each individual bit o d/a converter analog output port p15_0/rxd6 i sio6 receive data input pin p15_1/txd6 o sio6 transmit data output pin p15_2/rxc6 i/o sio6 receive clock i/o pin port p15_3/txc6 i/o 4-bit i/o port pull-up resistors can be specified for each individual bit i/o sio6 transmit clock i/o pin
pedl66577-01 1 semiconductor msm66577 family 9/34 function symbol type description v dd i power supply pin connect all v dd pins to the power supply.* gnd i gnd pin connect all gnd pins to gnd.* v ref i analog reference voltage pin power supply agnd i analog gnd pin xt0 i sub clock oscillation input pin connect to a crystal oscillator of f = 32.768 khz. xt1 o sub clock oscillation output pin connect to a crystal oscillator of f = 32.768 khz. the clock output is opposite in phase to xt0. osc0 i main clock oscillation input pin connect to a crystal or ceramic oscillator. or, input an external clock. oscillation osc1 o main clock oscillation output pin connect to a crystal or ceramic oscillator. the clock output is opposite in phase to osc0. leave this pin unconnected when an external clock is used. reset res i reset input pin nmi i non-maskable interrupt input pin ea i external program memory access input pin if the ea pin is enabled (low level), the internal program memory is masked and the cpu executes the program code in external program memory through all address space. other selmbus i selmbus = h: address/data separate bus type selmbus = l: multiplexed bus type * each of the family devices has unique pattern routes for the internal power and ground. connect the power supply voltage to all v dd pins and the ground potential to all gnd pins. if a device may have one or more v dd or gnd pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation.
pedl66577-01 1 semiconductor msm66577 family 10/34 absolute maximum ratings parameter symbol condition rating unit msm66577/q577 ?0.3 to +7.0 v digital power supply voltage v dd msm66577l/q577ly ?0.3 to +4.6 v input voltage v i ? ?0.3 to v dd + 0.3 v output voltage v o ? ?0.3 to v dd + 0.3 v analog reference voltage v ref ? ?0.3 to v dd + 0.3 v analog input voltage v ai gnd = agnd = 0 v ta = 25c ? ?0.3 to v ref v power dissipation p d ta = 70c per package 100-pin tqfp 650 mw storage temperature t stg ? ?50 to +150 c recommended operating conditions parameter symbol condition range unit msm66577 f osc 30 mhz 4.5 to 5.5 msm66q577 f osc 30 mhz 4.5 to 5.5 msm66577l f osc 14 mhz 2.4 to 3.6 digital power supply voltage v dd msm66q577ly f osc 14 mhz 3.0 to 3.6 v analog reference voltage v ref ?v dd ?0.3 to v dd v analog input voltage v ai ? agnd to v ref v memory hold voltage v ddh f osc = 0 hz 2.0 to 5.5 v msm66577 v dd = 4.5 to 5.5 v 2 to 30 msm66q577 v dd = 4.5 to 5.5 v 2 to 30 msm66577l v dd = 2.4 to 3.6 v 2 to 14 f osc msm66q577ly v dd = 3.0 to 3.6v 2 to 14 mhz operating frequency f xt ? 32.768 khz ambient temperature ta ? ?30 to +70 c mos load 20 ? p0, p3, p11 6 ? fan out n ttl load p1, p2, p4, p5, p6, p7, p8, p9, p10, p14, p15 1?
pedl66577-01 1 semiconductor msm66577 family 11/34 allowable output current values msm66577/q577 (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter pin symbol min. typ. max. unit ?h? output pin (1 pin) all output pins i oh ???2 ?h? output pins (sum total) sum total of all output pins i oh ? ? ?40 p0, p3, p11 10 ?l? output pin (1 pin) other ports i ol ?? 5 sum total of p0, p3, p11 80 sum total of p1, p2, p4 sum total of p5, p6, p9 sum total of p7, p8, p10, p14, p15 50 ?l? output pins (sum total) sum total of all output pins i ol ?? 140 ma [note] each of the family devices has unique pattern routes for the internal power and ground. connect the power supply voltage to all v dd pins and the ground potential to all gnd pins. if a device may have one or more v dd or gnd pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation. internal flash rom programming conditions parameter symbol condition rating unit msm66q577 4.5 to 5.5 supply voltage v dd msm66q577ly 3.0 to 3.6 v during read -30 to +70 ambient temperature ta during programming +0 to +50 c endurance cep ? 100 cycles blocks size ? ? 128 bytes
pedl66577-01 1 semiconductor msm66577 family 12/34 elelctrical characteristics dc characteristics 1 (v dd = 4.5 to 5.5 v) (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. typ. max. unit ?h? input voltage *1 0.44v dd ?v dd +0.3 ?h? input voltage *2,*3,*4,*5,*6 v ih ? 0.80v dd ?v dd +0.3 ?l? input voltage *1 ?0.3 ? 0.16v dd ?l? input voltage *2,*3,*4,*5,*6 v il ? ?0.3 ? 0.2v dd i o = ?400 a v dd ?0.4 ? ? ?h? output voltage *1, *2, *4 v oh i o = ?2.0 ma v dd ?0.6 ? ? i o = 3.2 ma ? ? 0.4 ?l? output voltage *1, *4 i o = 10.0 ma ? ? 0.8 i o = 1.6 ma ? ? 0.4 ?l? output voltage *2 v ol i o = 5.0 ma ? ? 0.8 v input leakage current *3 ? ? 1/?1 input current *5 ? ? 1/?250 input current *6 i ih /i il v i = v dd /0 v ? ? 15/?15 a output leakage current *1, *2, *4 i lo v o = v dd /0 v ? ? 10 a pull-up resistance r pull v i = 0 v 25 50 100 k ? input capacitance c i ?5? output capacitance c o f = 1 mhz, ta = 25c ?7? pf during a/d operation ? ? 4 ma analog reference supply current i ref when a/d is stopped ? ? 10 a *1: applicable to p0 *2: applicable to p1, p2, p4, p5, p6, p7, p8, p9, p10, p14, p15 *3: applicable to p12, selmbus, ea , nmi *4: applicable to p3, p11 *5: applicable to res *6: applicable to osc0 supply current (v dd =4.5 to 5.5 v) (v dd =4.5 to 5.5 v, ta=?30 to +70c) mode symbol condition min. typ. max. unit f=30 mhz ? 60 90 ma cpu operation mode *1 i dd f=32.768 khz ? 80 180 a halt mode *2 i ddh f=30 mhz ? 40 60 ma xt is used ? 5 110 osc is stopped xt is not used ? 1 100 stop mode *3 i dds osc is stopped, xt is not used v dd =2 v, ta=25c ?0.2 10 a [note] ports used as inputs are at v dd or 0 v. other ports are unloaded. *1. cpu and all the peripheral functions (timer, pwm, a/d, etc.) are activated. *2. cpu is stopped, and all the peripheral functions (timer, pwm, a/d, etc.) are activated. *3. cpu and all the peripheral functions are deactivated (the clock timer is being activated when the xt is used).
pedl66577-01 1 semiconductor msm66577 family 13/34 dc characteristics 2 (v dd = 2.4 to 3.6 v) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. typ. max. unit msm66577l 0.44v dd ?v dd +0.3 ?h? input voltage *1 msm66q577ly 0.55v dd ?v dd +0.3 ?h? input voltage *2,*3,*4,*5,*6 v ih ? 0.80v dd ?v dd +0.3 ?l? input voltage *1 ?0.3 ? 0.16v dd ?l? input voltage *2,*3,*4,*5,*6 v il ? ?0.3 ? 0.2v dd i o = ?400 a v dd ?0.4 ? ? ?h? output voltage *1, *4 i o = ?2.0 ma v dd ?0.8 ? ? i o = ?200 a v dd ?0.4 ? ? ?h? output voltage *2 v oh i o = ?1.0 ma v dd ?0.8 ? ? i o = 3.2 ma ? ? 0.5 ?l? output voltage *1, *4 i o = 5.0 ma ? ? 0.9 i o = 1.6 ma ? ? 0.5 ?l? output voltage *2 v ol i o = 2.5 ma ? ? 0.9 v input leakage current *3 ? ? 1/?1 input current *5 ? ? 1/?250 input current *6 i ih /i il v i = v dd /0 v ? ? 15/?15 a output leakage current *1, *2, *4 i lo v o = v dd /0 v ? ? 10 a pull-up resistance r pull v i = 0 v 40 100 200 k ? input capacitance c i ?5? output capacitance c o f = 1 mhz, ta = 25c ?7? pf during a/d operation ? ? 2 ma analog reference supply current i ref when a/d is stopped ? ? 5 a *1: applicable to p0 *2: applicable to p1, p2, p4, p5, p6, p7, p8, p9, p10, p14, p15 *3: applicable to p12 *4: applicable to p3, p11, selmbus, ea , nmi *5: applicable to res *6: applicable to osc0 supply current (v dd =2.4 to 3.6 v) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) mode symbol condition min. typ. max. unit f=14 mhz ? 15 30 ma cpu operation mode *1 i dd f=32.768 khz ? 50 150 a halt mode *2 i ddh f=14 mhz ? 10 20 ma xt is used* ? 3 110 osc is stopped xt is not used* ? 1 100 stop mode *3 i dds osc is stopped, xt is not used v dd =2 v, ta=25c* ?0.2 10 a [note] ports used as inputs are at v dd or 0 v. other ports are unloaded. *1. cpu and all the peripheral functions (timer, pwm, a/d, etc.) are activated. *2. cpu is stopped, and all the peripheral functions (timer, pwm, a/d, etc.) are activated. *3. cpu and all the peripheral functions are deactivated (the clock timer is being activated when the xt is used).
pedl66577-01 1 semiconductor msm66577 family 14/34 ac characteristics 1 (v dd = 4.5 to 5.5 v) (1) separate bus type external program memory control (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? clock pulse width (high level) t wh 13 ? clock pulse width (low level) t wl 13 ? psen pulse width t pw 2 t ? 15 ? psen pulse delay time t pd ?45 address setup time t as t ? 25 ? address hold time t ah 0? instruction setup time t is 25 ? instruction hold time t ih 0? read data access time t acc c l = 50 pf ?3 t ? 65 ns note: t = t cyc /2 inst0 to 7 pc0 to 19 bus timin g durin g no wait c y cle time t cyc t wh cpuclk psen a0 to a19 d0 to d7 t wl t pd t pw t as t acc t is t ih t ah
pedl66577-01 1 semiconductor msm66577 family 15/34 external data memory control (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? clock pulse width (high level) t wh 13 ? clock pulse width (low level) t wl 13 ? rd pulse width t rw 2 t ? 15 ? wr pulse width t ww 2 t ? 15 ? rd pulse delay time t rd ?45 wr pulse delay time t wd ?45 address setup time t as t ? 25 ? address hold time t ah t ? 3 ? read data setup time t rs 25 ? read data hold time t rh 0? read data access time t acc ?3t ?65 write data setup time t ws 2t ? 30 ? write data hold time t wh c l = 50 pf t ? 3 ? ns note: t = t cyc /2 din0 to 7 rap0 to 19 t rd t cyc t wh cpuclk rd a0 to a19 d0 to d7 dout0 to 7 rap0 to 19 bus timing during no wait cycle time wr a0 to a19 d0 to d7 t wl t rw t as t acc t rs t ww t wd t ah t rh t ah t as t ws t wh
pedl66577-01 1 semiconductor msm66577 family 16/34 (2) multiplexed bus type external program memory control (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? clock pulse width (high level) t wh 13 ? clock pulse width (low level) t wl 13 ? ale pulse width t aw 2 t ? 10 ? psen pulse width t pw 2 t ? 15 ? psen pulse delay time t pad t ? 3 ? low address setup time t als 2t ? 15 ? low address hold time t alh t ? 3 ? high address setup time t ahs 3t ? 25 ? high address hold time t ahh 0? instruction setup time t is 25 ? instruction hold time t ih c l = 50 pf 0t ? 3 ns note: t = t cyc /2 t cyc inst0 to 7 t wh cpuclk psen a8 to a19 ad0 to ad7 ale pc0 to 7 pc8 to 19 t wl t aw t pad t pw t als t alh t is t ih t ahs t ahh bus timing during no wait cycle time
pedl66577-01 1 semiconductor msm66577 family 17/34 external data memory control (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? clock pulse width (high level) t wh 13 ? clock pulse width (low level) t wl 13 ? ale pulse width t aw 2 t ? 10 ? rd pulse width t rw 2 t ? 15 ? wr pulse width t ww 2 t ? 15 ? rd pulse delay time t rad t ? 3 ? wr pulse delay time t wad t ? 3 ? low address setup time t als 2 t ? 15 ? low address hold time t alh t ? 3 ? high address setup time t ahs 3 t ? 25 ? high address hold time t ahh t ? 3 ? read data setup time t rs 25 ? read data hold time t rh 0t ? 3 write data setup time t ws 2t ? 30 ? write data hold time t wh c l = 50 pf t ? 3 ? ns note: t = t cyc /2 din0 to 7 rap8 to 19 a t cyc t wh cpuclk rd a8 to a19 ad0 to ad7 ale rap0 to 7 dout0 to 7 wr a8 to a19 ad0 to ad7 rap0 to 7 bus timin g durin g no wait c y cle time rap8 to 19 t wl t aw t rad t rw t als t alh t rs t rh t ahh t ahs t wad t ww t wh t ws t als t alh t ahh t ahs
pedl66577-01 1 semiconductor msm66577 family 18/34 (3) serial port control serial ports 1 and 6 (sio1 and 6) master mode (clock synchronous serial port) (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? serial clock cycle time t sckc 4 t cyc ? output data setup time t stmxs 2 t ? 5 ? output data hold time t stmxh 5 t ? 10 ? input data setup time t srmxs 13 ? input data hold time t srmxh c l = 50 pf 0? ns note: t = t cyc /2 t cyc cpuclk txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh
pedl66577-01 1 semiconductor msm66577 family 19/34 slave mode (clock synchronous serial port) (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? serial clock cycle time t sckc 4 t cyc ? output data setup time t stmxs 2 t ? 15 ? output data hold time t stmxh 4 t ? 10 ? input data setup time t srmxs 13 ? input data hold time t srmxh c l = 50 pf 3? ns note: t = t cyc /2 txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh t cyc cpuclk
pedl66577-01 1 semiconductor msm66577 family 20/34 serial ports 4 and 5 (sio4 and 5) master mode (clock synchronous serial port) (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? serial clock cycle time t sckc 6 t cyc ? output data setup time t stmxs 6 t ? 5 ? output data hold time t stmxh 4.5 t ? 10 ? input data setup time t srmxs 13 ? input data hold time t srmxh c l = 50 pf 0? ns note: t = t cyc /2 sdin (sioi) sdout (sioo) siock cpuclk t cyc t stmxs t stmxh t sckc t srmxs t srmxh
pedl66577-01 1 semiconductor msm66577 family 21/34 slave mode (clock synchronous serial port) (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 30 mhz 33.3 ? serial clock cycle time t sckc 6 t cyc ? output data setup time t stmxs 3 t ? 15 ? output data hold time t stmxh 6 t ? 10 ? input data setup time t srmxs 13 ? input data hold time t srmxh c l = 50 pf 3? ns note: t = t cyc /2 measurement points for ac timing (except the serial port) v dd 0 v 2.0 v 0.8 v 2.0 v 0.8 v measurement points for ac timing (the serial port) v dd 0v 0.8v dd 0.2v dd 0.8v dd 0.2v dd cpuclk (sioi) sdout (sioo) siock sdin t stmxs t stmxh t sckc t srmxs t srmxh t cyc
pedl66577-01 1 semiconductor msm66577 family 22/34 ac characteristics 2 (v dd = 2.4 to 3.6 v) (1) separate bus type external program memory control msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? clock pulse width (high level) t wh 28 ? clock pulse width (low level) t wl 28 ? psen pulse width t pw 2 t ? 40 ? psen pulse delay time t pd ?95 address setup time t as t ? 45 ? address hold time t ah 0? instruction setup time t is 75 ? instruction hold time t ih 0? read data access time t acc c l = 50 pf ?3 t ? 120 ns note: t = t cyc /2 inst0 to 7 pc0 to 19 bus timin g durin g no wait c y cle time t cyc t wh cpuclk psen a0 to a19 d0 to d7 t wl t pd t pw t as t acc t is t ih t ah
pedl66577-01 1 semiconductor msm66577 family 23/34 external data memory control msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? clock pulse width (high level) t wh 28 ? clock pulse width (low level) t wl 28 ? rd pulse width t rw 2 t ? 40 ? wr pulse width t ww 2 t ? 40 ? rd pulse delay time t rd ?95 wr pulse delay time t wd ?95 address setup time t as t ? 45 ? address hold time t ah t ? 6 ? read data setup time t rs 75 ? read data hold time t rh 0? read data access time t acc ?3t ?120 write data setup time t ws 2t ? 55 ? write data hold time t wh c l = 50 pf t ? 6 ? ns note: t = t cyc /2 din0 to 7 rap0 to 19 t rd t cyc t wh cpuclk rd a0 to a19 d0 to d7 dout0 to 7 rap0 to 19 bus timing during no wait cycle time wr a0 to a19 d0 to d7 t wl t rw t as t acc t rs t ww t wd t ah t rh t ah t as t ws t wh
pedl66577-01 1 semiconductor msm66577 family 24/34 (2) multiplexed bus type external program memory control msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? clock pulse width (high level) t wh 28 ? clock pulse width (low level) t wl 28 ? ale pulse width t aw 2 t ? 15 ? psen pulse width t pw 2 t ? 40 ? psen pulse delay time t pad t ? 6 ? low address setup time t als 2t ? 25 ? low address hold time t alh t ? 6 ? high address setup time t ahs 3t ? 45 ? high address hold time t ahh 0? instruction setup time t is 75 ? instruction hold time t ih c l = 50 pf 0t ? 6 ns note: t = t cyc /2 bus timing during no wait cycle time inst0 to 7 t cyc t wh cpuclk psen a8 to a19 ad0 to ad7 ale pc0 to 7 pc8 to 19 t wl t aw t pad t pw t als t alh t is t ih t ahs t ahh
pedl66577-01 1 semiconductor msm66577 family 25/34 external data memory control msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? clock pulse width (high level) t wh 28 ? clock pulse width (low level) t wl 28 ? ale pulse width t aw 2 t ? 15 ? rd pulse width t rw 2 t ? 40 ? wr pulse width t ww 2 t ? 40 ? rd pulse delay time t rad t ? 6 ? wr pulse delay time t wad t ? 6 ? low address setup time t als 2 t ? 25 ? low address hold time t alh t ? 6 ? high address setup time t ahs 3 t ? 45 ? high address hold time t ahh t ? 6 ? read data setup time t rs 75 ? read data hold time t rh 0t ? 6 write data setup time t ws 2t ? 55 ? write data hold time t wh c l = 50 pf t ? 6 ? ns note: t = t cyc /2 t cyc din0 to 7 rap8 to 19 a t wh cpuclk rd a8 to a19 ad0 to ad7 ale rap0 to 7 dout0 to 7 wr a8 to a19 ad0 to ad7 rap 0 to 7 bus timin g durin g no wait c y cle time rap8 to 19 t wl t aw t rad t rw t als t alh t rs t rh t ahh t ahs t wad t ww t wh t ws t als t alh t ahh t ahs
pedl66577-01 1 semiconductor msm66577 family 26/34 (3) serial port control serial ports 1 and 6 (sio1 and 6) master mode (clock synchronous serial port) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? serial clock cycle time t sckc 4 t cyc ? output data setup time t stmxs 2 t ? 10 ? output data hold time t stmxh 5 t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 0? ns note: t = t cyc /2 sdin (rxd) sdout (txd) txc/rxc cpuclk t cyc t stmxs t stmxh t sckc t srmxs t srmxh
pedl66577-01 1 semiconductor msm66577 family 27/34 slave mode (clock synchronous serial port) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter s y mbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? serial clock cycle time t sckc 4 t cyc ? output data setup time t stmxs 2 t ? 30 ? output data hold time t stmxh 4 t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 7? ns note: t = t cyc /2 t cyc txc/rxc sdout (txd) sdin (rxd) t stmxs t stmxh t sckc t srmxs t srmxh cpuclk
pedl66577-01 1 semiconductor msm66577 family 28/34 serial ports 4 and 5 (sio4 and 5) master mode (clock synchronous serial port) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? serial clock cycle time t sckc 5.6 t cyc ? output data setup time t stmxs 5.6 t ? 10 ? output data hold time t stmxh 4.2 t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 0? ns note: t = t cyc /2 sdin (sioi) sdout (sioo) siock cpuclk t cyc t stmxs t stmxh t sckc t srmxs t srmxh
pedl66577-01 1 semiconductor msm66577 family 29/34 slave mode (clock synchronous serial port) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. max. unit cycle time t cyc f osc = 14 mhz 71.4 ? serial clock cycle time t sckc 5.6 t cyc ? output data setup time t stmxs 2.8 t ? 30 ? output data hold time t stmxh 5.6 t ? 20 ? input data setup time t srmxs 21 ? input data hold time t srmxh c l = 50 pf 7? ns note: t = t cyc /2 measurement points for ac timing (except the serial port) v dd 0v 0.44v dd 0.16v dd 0.44v dd 0.16v dd measurement points for ac timing (the serial port) v dd 0v 0.8v dd 0.2v dd 0.8v dd 0.2v dd cpuclk (sioi) sdout (sioo) siock sdin t stmxs t stmxh t sckc t srmxs t srmxh t cyc
pedl66577-01 1 semiconductor msm66577 family 30/34 a/d converter characteristics 1 (v dd = 4.5 to 5.5 v) (ta = ?30 to 70c, v dd = v ref = 4.5 to 5.5 v, agnd = gnd = 0 v) parameter symbol condition min. typ. max. unit resolution n ? 10 ? bit linearity error e l ??3 differential linearity error e d ??2 zero scale error e zs ??+3 full-scale error e fs refer to measurement circuit 1 analog input source impedance r i 5 k ? t conv = 10.7 s ???3 cross talk e ct refer to measurement circuit 2 ??1 lsb conversion time t conv set according to adtm set data 10.7 ? ? s/ch a/d converter characteristics 2 (v dd = 2.4 to 3.6 v) msm66577l (ta = ?30 to 70c, v dd = v ref = 2.4 to 3.6 v, agnd = gnd = 0 v) msm66q577ly (ta = ?30 to 70c, v dd = v ref = 3.0 to 3.6 v, agnd = gnd = 0 v) parameter symbol condition min. typ. max. unit resolution n ? 10 ? bit linearity error e l ??4 differential linearity error e d ??3 zero scale error e zs ??+4 full-scale error e fs refer to measurement circuit 1 analog input source impedance r i 5 k ? t conv = 10.7 s ???4 cross talk e ct refer to measurement circuit 2 ??2 lsb conversion time t conv set according to adtm set data 27.4 ? ? s/ch v ref reference voltage v dd gnd ? + analog input r i ai0 to ai7 c i 0.1 f 47 f + 0.1 f 47 f + +5 v / +3v 0 v agnd r i (impedance of analog input source) 5 k ? c i ? 0.1 f measurement circuit 1
pedl66577-01 1 semiconductor msm66577 family 31/34 measurement circuit 2 definition of terminology 1. resolution resolution is the value of minimum discernible analog input. with 10 bits, since 2 10 = 1024, resolution of (v ref ? agnd) 1024 is possible. 2. linearity error linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit a/d converter (not including quantization error). ideal conversion characteristics can be obtained by dividing the voltage between v ref and agnd into 1024 equal steps. 3. differential linearity error differential linearity error indicates the smoothness of conversion characteristics. ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1lsb = (v ref ? agnd) 1024. differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. zero scale error zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000h to 001h. 5. full-scale error full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3feh to 3ffh. ? + analog input 5 k ? 0.1 f ai0 ai1 ai7 cross talk is the difference between the a/d conversion results when the same analog input is applied to ai0 through ai7 and the a/d conversion results of the circuit to the left. to v ref or agnd
pedl66577-01 1 semiconductor msm66577 family 32/34 d/a converter characteristics msm66577/q577 (v dd = 4.5 to 5.5 v, ta = ?30 to +70c) msm66577l (v dd = 2.4 to 3.6 v, ta = ?30 to +70c) msm66q577ly (v dd = 3.0 to 3.6 v, ta = ?30 to +70c) parameter symbol condition min. typ. max. unit resolution n ? ? 8 bit linearity error e l ??1 absolute precision ? ? ??2 lsb conversion time t conv c l = 50 pf ? 20 50 s analog output impedance ? ? ? 20 ? k ? definition of terminology 1. resolution resolution is the value of minimum discernible analog output. with 8 bits, since 2 8 = 256, resolution of (v dd ? gnd) 256 is possible. 2. linearity error linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of an 8-bit d/a converter. ideal conversion characteristics can be obtained by dividing the voltage between v dd and gnd into 256 equal steps. 3. differential linearity error differential linearity error indicates the smoothness of conversion characteristics. ideally, the range of analog input voltage that corresponds to 1 converted bit of digital input is 1lsb = (v dd ? gnd) 256. differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. absolute precision absolute precision is a gross error including a linearity error and the effect of noise.
pedl66577-01 1 semiconductor msm66577 family 33/34 package dimensions (unit: mm) tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the surface mount type packages the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
pedl66577-01 1 semiconductor msm66577 family 34/34 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2000 oki electric industry co., ltd.

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